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Low Distortion Differential RF/IF Amplifier AD8351
FEATURES -3 dB Bandwidth of 2.2 GHz for AV = 12 dB Single Resistor Programmable Gain 0 dB AV 26 dB Differential Interface Low Noise Input Stage 2.7 nV/Hz @ AV = 10 dB Low Harmonic Distortion -79 dBc Second @ 70 MHz -81 dBc Third @ 70 MHz OIP3 of 31 dBm @ 70 MHz Single-Supply Operation: 3 V to 5.5 V Low Power Dissipation: 28 mA @ 5 V Adjustable Output Common-Mode Voltage Fast Settling and Overdrive Recovery Slew Rate of 13,000 V/ s Power-Down Capability 10-Lead MSOP Package APPLICATIONS Differential ADC Drivers Single-Ended-to-Differential Conversion IF Sampling Receivers RF/IF Gain Blocks SAW Filter Interfacing FUNCTIONAL BLOCK DIAGRAM
AD8351
VOCM
PWUP
BIAS CELL
VPOS
RGP1
INHI
INLO
RGP2
OPHI
OPLO
COMM
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
-110
AD8351 WITH 10 dB OF GAIN DRIVING THE AD6645 (RL = 1k ) ANALOG INPUT: 70MHz ENCODE : 80MHz SNR : 69.1dB FUND : -1.1dBFS HD2 : -78.5dBc HD3 : -80.7dBc THD : -75.9dBc SFDR : 78.2dBc
INHI
100nF 25
RG 200
INLO
AD8351 AD8351
100nF 25
AD6645 14-BIT ADC
2
+
3
-120
-130
0
5
10
15
20
25
30
35
GENERAL DESCRIPTION
The AD8351 is a low cost differential amplifier useful in RF and IF applications up to 2.2 GHz. The voltage gain can be set from unity to 26 dB using a single external gain resistor. The AD8351 provides a nominal 150 differential output impedance. The excellent distortion performance and low noise characteristics of this device allow for a wide range of applications. The AD8351 is designed to satisfy the demanding performance requirements of communications transceiver applications. The device can be used as a general-purpose gain block, an ADC driver,
and a high speed data interface driver, among other functions. The AD8351 can also be used as a single-ended-to-differential amplifier with similar distortion products as in the differential configuration. The exceptionally good distortion performance makes the AD8351 an ideal solution for 12-bit and 14-bit IF sampling receiver designs. Fabricated in ADI's high speed XFCB process, the AD8351 has high bandwidth that provides high frequency performance and low distortion. The quiescent current of the AD8351 is 28 mA typically. The AD8351 amplifier comes in a compact 10-lead MSOP package and will operate over the temperature range of -40C to +85C.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2004 Analog Devices, Inc. All rights reserved.
(V = 5 V, R = 150 , = 110 (A = noted AD8351-SPECIFICATIONS specified differentially,Runless otherwise10 dB),.)f = 70 MHz, T = 25 C, parameters
S L G V
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth
Conditions GAIN = 6 dB, VOUT 1.0 V p-p GAIN = 12 dB, VOUT 1.0 V p-p GAIN = 18 dB, VOUT 1.0 V p-p 0 dB GAIN 20 dB, VOUT 1.0 V p-p 0 dB GAIN 20 dB, VOUT 1.0 V p-p Using 1% Resistor for RG, 0 dB AV 20 dB VS 5% -40C to +85C RL = 1 k, VOUT = 2 V Step RL = 150 , VS = 2 V Step 1 V Step to 1% VIN = 4 V to 0 V Step, VOUT 10 mV
Min
Typ 3,000 2,200 600 200 400 1 0.08 3.9 13,000 7,500 <3 <2 -67
Max
Unit MHz MHz MHz MHz MHz dB dB/V mdB/C V/ s V/ s ns ns dB
Bandwidth for 0.1 dB Flatness Bandwidth for 0.2 dB Flatness Gain Accuracy Gain Supply Sensitivity Gain Temperature Sensitivity Slew Rate Settling Time Overdrive Recovery Time Reverse Isolation (S12)
INPUT/OUTPUT CHARACTERISTICS Input Common-Mode Voltage Adjustment Range Max Output Voltage Swing 1 dB Compressed Output Common-Mode Offset Output Common-Mode Drift -40C to +85C Output Differential Offset Voltage Output Differential Offset Drift -40C to +85C Input Bias Current Input Resistance1 Input Capacitance1 CMRR Output Resistance1 Output Capacitance1 POWER INTERFACE Supply Voltage PWUP Threshold PWUP Input Bias Current Quiescent Current 3 PWUP at 5 V PWUP at 0 V
1.2 to 3.8 4.75 40 0.24 20 0.13 15 5 0.8 43 150 0.8 5.5 1.3 100 25 28
V V p-p mV mV/C mV mV/C A k pF dB pF V V A A mA
32
-2-
REV. B
AD8351
Parameter NOISE/DISTORTION 10 MHz Second/Third Harmonic Distortion2 Third-Order IMD Conditions Min Typ Max Unit
Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point 70 MHz Second/Third Harmonic Distortion2 Third-Order IMD
RL = 1 k, VOUT = 2 V p-p RL = 150 , VOUT = 2 V p-p RL = 1 k, f1 = 9.5 MHz, f2 = 10.5 MHz, VOUT = 2 V p-p Composite RL = 150 , f1 = 9.5 MHz, f2 = 10.5 MHz, VOUT = 2 V p-p Composite f1 = 9.5 MHz, f2 = 10.5 MHz
-95/-93 -86/-71 -90 -70 33 2.65 13.5
dBc dBc dBc dBc dBm nV/Hz dBm
Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point 140 MHz Second/Third Harmonic Distortion2 Third-Order IMD
RL = 1 k, VOUT = 2 V p-p RL = 150 , VOUT = 2 V p-p RL = 1 k, f1 = 69.5 MHz, f2 = 70.5 MHz, VOUT = 2 V p-p Composite RL = 150 , f1 = 69.5 MHz, f2 = 70.5 MHz, VOUT = 2 V p-p Composite f1 = 69.5 MHz, f2 = 70.5 MHz
-79/-81 -65/-66 -85 -69 31 2.70 13.3
dBc dBc dBc dBc dBm nV/Hz dBm
Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point 240 MHz Second/Third Harmonic Distortion2 Third-Order IMD
RL = 1 k, VOUT = 2 V p-p RL = 150 , VOUT = 2 V p-p RL = 1 k, f1 = 139.5 MHz, f2 = 140.5 MHz, VOUT = 2 V p-p Composite RL = 150 , f1 = 139.5 MHz, f2 = 140.5 MHz, VOUT = 2 V p-p Composite f1 = 139.5 MHz, f2 = 140.5 MHz
-69/-69 -54/-53 -79 -67 29 2.75 13
dBc dBc dBc dBc dBm nV/Hz dBm
Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point
RL = 1 k, VOUT = 2 V p-p RL = 150 , VOUT = 2 V p-p RL = 1 k, f1 = 239.5 MHz, f2 = 240.5 MHz, VOUT = 2 V p-p Composite RL = 150 , f1 = 239.5 MHz, f2 = 240.5 MHz, VOUT = 2 V p-p Composite f1 = 239.5 MHz, f2 = 240.5 MHz
-60/-66 -46/-50 -76 -62 27 2.90 13
dBc dBc dBc dBc dBm nV/Hz dBm
NOTES 1 Values are specified differentially. 2 See Applications section for single-ended-to-differential performance. Specifications subject to change without notice.
REV. B
-3-
AD8351
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
PWUP 1 RGP1 2 INHI 3
10 VOCM
Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V PWUP Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPOS Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 320 mW JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125C/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125C Operating Temperature Range . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AD8351
9
VPOS
8 OPHI TOP VIEW INLO 4 (Not to Scale) 7 OPLO
RGP2 5
6
COMM
ORDERING GUIDE
Model AD8351ARM AD8351ARM-R2 AD8351ARM-REEL7 AD8351-EVAL
Temp. Range -40C to +85C -40C to +85C -40C to +85C
Package Description 10-Lead MSOP, 7" Tape and Reel 10-Lead MSOP, 7" Tape and Reel 10-Lead MSOP, 7" Tape and Reel Evaluation Board
Package Option RM-10 RM-10 RM-10
Branding JDA JDA JDA
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3 4 5 6 7 8 9 10
Name PWUP RGP1 INHI INLO RGP2 COMM OPLO OPHI VPOS VOCM
Function Apply a positive voltage (1.3 V VPWUP VPOS ) to activate device. Gain Resistor Input 1. Balanced Differential Input. Biased to midsupply, typically ac-coupled Balanced Differential Input. Biased to midsupply, typically ac-coupled. Gain Resistor Input 2. Device Common. Connect to low impedance ground. Balanced Differential Output. Biased to VOCM, typically ac-coupled. Balanced Differential Output. Biased to VOCM, typically ac-coupled. Positive Supply Voltage. 3 V to 5.5 V. Voltage applied to this pin sets the common-mode voltage at both the input and output. Typically decoupled to ground with a 0.1 F capacitor.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8351 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-4-
REV. B
Typical Performance Characteristics- AD8351
(VS = 5 V, T = 25 C, unless otherwise noted.)
20 RG = 20
30
RG = 10
15 RG = 80
25
20
GAIN (dB)
GAIN (dB)
10 RG = 200 5
RG = 50
15 RG = 200 10
0
5
-5
1
10
100 FREQUENCY (MHz)
1000
10000
0
1
10
100 FREQUENCY (MHz)
1000
10000
TPC 1. Gain vs. Frequency for a 150 Differential Load (AV = 6 dB, 12 dB, and 18 dB)
35
30
TPC 4. Gain vs. Frequency for a 1 k Differential Load (AV = 10 dB, 18 dB, and 26 dB)
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 1
RL = 1k
25
20
GAIN (dB)
GAIN FLATNESS (dB)
15
10
RL = 150 RL = 150 RL = 1k
RL = OPEN
5
0 RL = 150
-5
RL = 1k
-10 10
100 RG ( )
1k
10k
10 100 FREQUENCY (MHz)
1000
TPC 2. Gain vs. Gain Resistor, RG (f = 100 MHz, RL = 150 , 1 k, and Open)
0
10.75 10.50
TPC 5. Gain Flatness vs. Frequency (RL = 150 and 1 k, AV =10 dB)
-10
10.50
GAIN (RL = 1k ) (dB)
10.25
GAIN (RL = 150 ) (dB)
-20
ISOLATION (dB)
-30 -40 -50 -60 -70 -80 -90
10.25
10.00
10.00
9.75
9.75
9.50
9.50
9.25
9.25 -50
-30
-10
10 30 50 TEMPERATURE ( C)
70
90
9.00 110
0
100
200
300
400 500 600 700 FREQUENCY (MHz)
800
900
1000
TPC 3. Gain vs. Temperature at 100 MHz (AV = 10 dB)
TPC 6. Isolation vs. Frequency (AV = 10 dB)
REV. B
-5-
AD8351
-30 -45
-50
HARMONIC DISTORTION (VPOS = 5V) (dBc)
HARMONIC DISTORTION (VPOS = 3V) (dBc)
-40
HD3
-55 HD2 HD2
-55
HARMONIC DISTORTION (dBc)
-60 -65 -70 -75
SINGLE-ENDED INPUT
-50 -60 -70
-65
-75 -85 HD3 -95 DIFFERENTIAL INPUT -105 -115 250
HD3 HD2
-80 -85 HD3 -90 -95
-80
-90
-100 0 25 50 75 100 125 150 175 FREQUENCY (MHz) 200 225
-100 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (MHz)
TPC 7. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 1 k (AV = 10 dB, at 3 V and 5 V Supplies)
0 -20
TPC 10. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 1 k Using Single-Ended Input (AV = 10 dB)
-50
HARMONIC DISTORTION (VPOS = 5V) (dBc)
HARMONIC DISTORTION (VPOS = 3V) (dBc)
-10 -20 -30 HD2 -40 -50 -60 -70 HD3
HD3
-30 -40 -50 -60 -70 -80 -90 DIFFERENTIAL INPUT
-55 SINGLE-ENDED INPUT
HARMONIC DISTORTION (dBc)
-60 -65 HD3 -70 -75 -80 -85 HD2 -90 -95 -100 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (MHz)
-80 -90 0 25 50
HD2
-100 -110 250
75
100 125 150 175 FREQUENCY (MHz)
200
225
TPC 8. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 150 (AV = 10 dB, at 3 V and 5 V Supplies)
3.00
NOISE SPECTRAL DENSITY (nV/ Hz)
TPC 11. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 150 Using Single-Ended Input (AV = 10 dB)
3.00 2.95
NOISE SPECTRAL DENSITY (nV/ Hz)
2.95 2.90 2.85 2.80 2.75 2.70 2.65 2.60 2.55 2.50 0 50 100 150 FREQUENCY (MHz) 200 250
2.90 2.85 2.80 2.75 2.70 2.65 2.60 2.55 2.50 0 50 100 150 FREQUENCY (MHz) 200 250
TPC 9. Noise Spectral Density (RTI) vs. Frequency (RL = 150 , 5 V Supply, AV = 10 dB)
TPC 12. Noise Spectral Density (RTI) vs. Frequency (RL = 150 , 3 V Supply, AV = 10 dB)
-6-
REV. B
AD8351
16 14 -70
OUTPUT 1dB COMPRESSION (dBm)
10 8 6 4 2 0 RL = 150 VPOS = 3V RL = 1k
THIRD-ORDER IMD (dBc)
100 125 150 175 200 225 250
12
RL = 150 VPOS = 5V RL = 1k
-75
-80
-85
-90
0
25
50
75
-95
0
25
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 13. Output Compression Point, P1 dB, vs. Frequency (RL = 150 and 1 k, AV = 10 dB, at 3 V and 5 V Supplies)
16 VPOS = 5V 14
TPC 16. Third-Order Intermodulation Distortion vs. Frequency for a 2 V p-p Composite Signal into RL = 1 k (AV = 10 dB, at 5 V Supplies)
-50
OUTPUT 1dB COMPRESSION (dBm)
-55
VPOS = 3V 10 8 6 4 2 0 0 100 GAIN RESISTOR ( ) 1000
THIRD-ORDER IMD (dBc)
12
-60
-65
-70
-75
0
25
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
TPC 14. Output Compression Point, P1 dB, vs. RG (f = 100 MHz, RL = 150 , AV = 10 dB, at 3 V and 5 V Supplies)
TPC 17. Third-Order Intermodulation Distortion vs. Frequency for a 2 V p-p Composite Signal into RL = 150 (AV = 10 dB, at 5 V Supplies)
13.29
13.30
13.31
13.32
13.33
13.34
13.35
13.36
13.37
13.38
13.39
13.40
13.41
-68.0 -68.2 -68.4 -68.6 -68.6 -68.8 -69.0 -69.2 -69.4 -69.6 -69.8 THIRD-ORDER INTERMODULATION DISTORTION (dBc)
OUTPUT 1dB COMPRESSION (dB)
TPC 15. Output Compression Point Distribution (f = 70 MHz, RL = 150 , AV = 10 dB)
TPC 18. Third-Order Intermodulation Distortion Distribution (f = 70 MHz, RL = 150 , AV = 10 dB)
REV. B
-7-
AD8351
4000 3500
IMPEDANCE MAGNITUDE ( )
0
3000 2500 2000 1500 1000 500 0 10
-25
PHASE (deg)
-50
3GHz
10MHz
10MHz
WITH 500MHz 500MHz 50 3GHz TERMINATIONS WITHOUT TERMINATIONS
-75
100 FREQUENCY (MHz)
-100 1000
TPC 19. Input Impedance vs. Frequency
TPC 22. Input Reflection Coefficient vs. Frequency (RS = RL = 100 with and without 50 Terminations)
160
30
150
25
IMPEDANCE MAGNITUDE ( )
140
20
IMPEDANCE PHASE (deg)
500MHz
130
15
10MHz
120
10
3GHz
110
5
100 0 100 FREQUENCY (MHz)
0 1000
TPC 20. Output Impedance vs. Frequency
TPC 23. Output Reflection Coefficient vs. Frequency (RS = RL = 100 )
80
0 -2 -4 -6
PHASE (deg)
-8 -10 -12 -14 -16 -18
0
25
50
75
100
125
150
175
200
225
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 250
70
GROUP DELAY (ps)
60
RL = 150 RL = 1k
CMRR (dB)
50
40
30
20 0 10 100 FREQUENCY (MHz) 1000
FREQUENCY (MHz)
TPC 21. Phase and Group Delay (AV = 10 dB, at 5 V Supplies)
TPC 24. Common-Mode Rejection Ratio, CMRR (RS = 100 )
-8-
REV. B
AD8351
0.6 0pF 0.4 2pF 0.2 5pF
0.50 1.00 0.75
10pF
VOLTAGE (V)
VOLTAGE (V)
0.25 0 -0.25 -0.50
0
-0.2
-0.4
-0.75 -1.00
-0.6 15
16
17
18
19
20 TIME (ns)
21
22
23
24
25
0
0.5
1.0
1.5
2.0 TIME (ns)
2.5
3.0
3.5
4.0
TPC 25. Transient Response under Capacitive Loading (RL = 150 , CL = 0 pF, 2 pF, 5 pF, 10 pF)
5.0 4.5 4.0 3.5
TPC 28. Large Signal Transient Response for a 1 V p-p Output Step (AV = 10 dB, RIP = 25 )
5 4 3 2
SETTLING (%)
OUTPUT (V)
3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 TIME (ns) 30 35 40
1 0 -1 -2 -3 -4 -5 0 3 6 TIME (ns) 9 12 15
TPC 26. 2
3
Output Overdrive Recovery (RL = 150 , AV = 10 dB)
VOUT
TPC 29. 1% Settling Time for a 2 V p-p Step (AV = 10 dB, RL = 150 )
2
1
VOLTAGE (V)
VIN 0
-1
-2
-3 0 5 10 15 20 25 30 TIME (ns) 35 40 45 50
TPC 27. Overdrive Recovery Using Sinusoidal Input Waveform RL = 150 (AV = 10 dB, at 5 V Supplies)
REV. B
-9-
AD8351
BASIC CONCEPTS COMMON-MODE ADJUSTMENT
Differential signaling is used in high performance signal chains, where distortion performance, signal-to-noise ratio, and low power consumption is critical. Differential circuits inherently provide improved common-mode rejection and harmonic distortion performance as well as better immunity to interference and ground noise.
1
PWUP RGP1 INHI INLO RGP2
VOCM 10 VPOS 9
The output common-mode voltage level is the dc offset voltage present at each of the differential outputs. The ac signals are of equal amplitude with a 180 phase difference but are centered at the same common-mode voltage level. The common-mode output voltage level can be adjusted from 1.2 V to 3.8 V by driving the desired voltage level into the VOCM pin, as illustrated in Figure 2.
0.1 F VS
2
3
OPHI OPLO
A 8
BALANCED SOURCE
RG
4
RL
7 A
2A
1
PWUP RGP1 INHI INLO RGP2
VOCM 10 VPOS 9 OPHI 8 RL OPLO
7
2
VOCM CDECL 1.2V 0.1 F TO 3.8V
5
COMM 6
3
Figure 1. Differential Circuit Representation
BALANCED SOURCE
RG
4
Figure 1 illustrates the expected input and output waveforms for a typical application. Usually the applied input waveform will be a balanced differential drive, where the signal applied to the INHI and INLO pins are equal in amplitude and differ in phase by 180. In some applications, baluns may be used to transform a singleended drive signal to a differential signal. The AD8351 may also be used to transform a single-ended signal to a differential signal.
GAIN ADJUSTMENT
5
COMM 6
Figure 2. Common-Mode Adjustment
INPUT AND OUTPUT MATCHING
The differential gain of the AD8351 is set using a single external resistor, RG, which is connected between Pins 2 and 5. The gain can be set to any value between 0 dB and 26 dB using the resistor values specified in TPC 2, with common gain values provided in Table I. The board traces used to connect the external gain resistor should be balanced and as short as possible to help prevent noise pickup and to ensure balanced gain and stability. The low frequency voltage gain of the AD8351 can be modeled as
AV = RL x RG (5.6) + 9.2 x RF x RL = VOUT VIN
RG x RL x 4.6 + 19.5 x RG + ( RL + RF ) x (39 + RG )
where: RF is 350 (internal). RL is the single-ended load resistance. RG is the gain setting resistor.
Table I. Gain Resistor Selection for Common Gain Values (Load Resistance Is Specified as Single-Ended)
The AD8351 provides a moderately high differential input impedance of 5 k. In practical applications, the input of the AD8351 will be terminated to a lower impedance to provide an impedance match to the driving source, as depicted in Figure 3. The terminating resistor, RT, should be as close as possible to the input pins in order to minimize reflections due to impedance mismatch. The 150 output impedance may need to be transformed to provide the desired output match to a given load. Matching components can be calculated using a Smith Chart or by using a resonant approach to determine the matching network that results in a complex conjugate match. The input and output impedances and reflection coefficients are provided in TPCs 19, 20, 22, and 23. For additional information on reactive matching to differential sources and loads, refer to the Applications section of the AD8350 data sheet. Figure 3 illustrates a SAW (surface acoustic wave) filter interface. Many SAW filters are inherently differential, allowing for a low loss output match. In this example, the SAW filter requires a 50 source impedance in order to provide the desired center frequency and Q. The series L shunt C output network provides a 150 to 50 impedance transformation at the desired frequency of operation. The impedance transformation is illustrated on a Smith Chart in Figure 4. It is possible to drive a single-ended SAW filter simply by connecting the unused output to ground using the appropriate terminating resistance. The overall gain of the system will be reduced by 6 dB due to the fact that only half of the signal will be available to the input of the SAW filter.
Gain, AV 0 dB 6 dB 10 dB 20 dB
RG (RL = 75 680 200 100 22
)
RG (RL = 500 2 k 470 200 43
)
VPOS RS BALANCED SOURCE RS RT 0.1 F 0.1 F LS 27nF CP 8pF LS 27nF 50 190MHz SAW
RS = RT 0.1 F RG RT
AD8351
150 0.1 F
Figure 3. Example of Differential SAW Filter Interface (fC = 190 MHz)
-10-
REV. B
AD8351
50 100
7 6 5
25
10
200
RF (k )
4 RL = 1000 3 RL = 500 2 RL = 150 1 0
500 50 150
500 200
0
SHUNT C SERIES L
100 50 25 10
0
100 RG ( )
1000
Figure 6b. Feedback Resistor Selection Figure 4. Smith Chart Representation of SAW Filter Output Matching Network
50 50 0.1 F RG 0.1 F 25 RF 0.1 F
ADC DRIVING
AD8351
0.1 F
RL
Figure 5. Single-Ended Application
SINGLE-ENDED-TO-DIFFERENTIAL OPERATION
The AD8351 can easily be configured as a single-ended-todifferential gain block, as illustrated in Figure 5. The input signal is ac-coupled and applied to the INHI input. The unused input is ac-coupled to ground. The values of C1 through C4 should be selected such that their reactances are negligible at the desired frequency of operation. To balance the outputs, an external feedback resistor, RF, is required. To select the gain resistor and the feedback resistor, refer to Figures 6a and 6b. From Figure 6a, select an RG for the required dB gain at a given load. Next, select from Figure 6b an RF resistor for the selected RG and load. Even though the differential balance is not perfect under these conditions, the distortion performance is still impressive. TPCs 10 and 11 show the second and third harmonic distortion performance when driving the input of the AD8351 using a single-ended 50 source.
35
The circuit in Figure 7 represents a simplified front end of the AD8351 driving the AD6645, which is a 14-bit, 105 MSPS A/D converter. For optimum performance, the AD6645 and the AD8351 are driven differentially. The resistors R1 and R2 present a 50 differential input impedance to the source with R3 and R4 providing isolation from the A/D input. The gain setting resistor for the AD8351 is RG. The AD6645 presents a 1 k differential load to the AD8351 and requires a 2.2 V p-p differential signal between AIN and AIN for a full-scale output. This AD8351 circuit then provides the gain, isolation, and source matching for the AD6645. The AD8351 also provides a balanced input, not provided by the balun, to the AD6645, which is essential for second-order cancellation. The signal generator is bipolar, centered around ground. Connecting the VOCM pin (10) of the AD8351 to the VREF pin of the AD6645 sets the common-mode output voltage of the AD8351 at 2.4 V. This voltage is bypassed with a 0.1 F capacitor. Increasing the gain of the AD8351 will increase the system noise and thus decrease the SNR but will not significantly affect the distortion. The circuit in Figure 7 can provide SFDR performance of better than -90 dBc with a 10 MHz input and -80 dBc with a 70 MHz input at a gain of 10 dB.
100nF 25 BALANCE 50 SOURCE 100nF 25
INHI OPHI RG
25 AIN
AD8351
OPLO 25 VOCM
AD6645
AIN VREF DIGITAL OUT
INLO
30 RL = 1000 25
Figure 7. ADC Driving Application Using Differential Input
GAIN (dB) 20 RL = 150 15 10
5 RL = 500 0 0 100 RG ( ) 1000
The circuit of Figure 8 represents a single-ended input to differential output configuration of the AD8351 driving the AD6645. In this case, R1 provides the input impedance. RG is the gain setting resistor. The resistor RF is required to balance the output voltages required for second-order cancellation by the AD6645 and can be selected using a chart. (See the Single-Ended-toDifferential Operation section.) The circuit depicted in Figure 8 can provide SFDR performance of better than -90 dBc with a 10 MHz input and -77 dBc with a 70 MHz input.
Figure 6a. Gain Selection
REV. B
-11-
AD8351
RF
I/O CAPACITIVE LOADING
OPHI 25 AIN
INHI SINGLEENDED 50 SOURCE R1 50 100nF RG INLO 25 100nF VOCM
AD8351
OPLO 25
AD6645
AIN VREF DIGITAL OUT
100nF
Figure 8. ADC Driving Application Using Single-Ended Input
ANALOG MULTIPLEXING
The AD8351 can be used as an analog multiplexer in applications where it is desirable to select multiple high speed signals. The isolation of each device when in a disabled state (PWUP pin pulled low) is about 60 dBc for the maximum input level of 0.5 V p-p out to 100 MHz. The low output noise spectral density allows for a simple implementation as depicted in Figure 9. The PWUP interface can be easily driven using most standard logic interfaces. By using an N-bit digital interface, up to N devices can be controlled. Output loading effects and noise need to be considered when using a large number of input signal paths. Each disabled AD8351 presents approximately a 700 load in parallel with the 150 output source impedance of the enabled device. As the load increases due to the addition of N devices, the distortion performance will degrade due to the heavier loading. Distortion better than -70 dBc can be achieved with four devices muxed into a 1 k load for signal frequencies up to 70 MHz.
BIT 1 INHI RGP1 SIGNAL INPUT 1 RG RGP2 INLO OPLO BIT 2 INHI RGP1 SIGNAL INPUT 2 RG RGP2 INLO OPLO PWUP OPHI PWUP OPHI N-BIT DIGITAL INTERFACE
Input or output direct capacitive loading greater than a few picofarads can result in excessive peaking and/or oscillation outside the pass band. This results from the package and bond wire inductance resonating in parallel with the input/output capacitance of the device and the associated coupling that results internally through the ground inductance. For low resistive load or source resistance, the effective Q is lower, and higher relative capacitance termination(s) can be allowed before oscillation or excessive peaking occurs. These effects can be eliminated by adding series input resistors (RIP) for high source capacitance, or series output resistors (ROP) for high load capacitance. Generally less than 25 is all that is required for I/O capacitive loading greater than ~2 pF. The higher the C, the smaller the R parasitic suppression resistor required. In addition, RIP also helps to reduce low gain in-band peaking, especially for light resistive loads.
CSTRAY CL RL 1k ROP
RIP RG
ROP
AD8351
CSTRAY
RIP
CL
Figure 10. Input and Output Parasitic Suppression Resistors, RIP and ROP, Used to Suppress Capacitive Loading Effects
AD8351
Due to package parasitic capacitance on the RG ports, high RG values (low gain) cause high ac-peaking inside the pass band, resulting in poor settling in the time domain. As an example, when driving a 1 k load, using 25 for RIP reduces the peaking by ~7 dB for RG equal to 200 (AV = 10 dB) (see Figure 11).
AD8351
MUX OUTPUT LOAD
BIT N INHI RGP1 SIGNAL INPUT N RG RGP2 INLO OPLO PWUP OPHI
AD8351
Figure 9. Using Several AD8351s to Form an N-Channel Analog MUX
Figure 11. Reducing Gain Peaking with Parasitic Suppressing Resistors (RIP = 25 , RL = 1 k)
-12-
REV. B
AD8351
It is important to ensure that all I/O, ground, and RG port traces be kept as short as possible. In addition, it is required that the ground plane be removed from under the package. Due to the inverse relationship between the gain of the device and the value of the RG resistor, any parasitic capacitance on the RG ports can result in gain-peaking at high frequencies. Following the precautions outlined in Figure 12 will help to reduce parasitic board capacitance, thus extending the device's bandwidth and reducing potential peaking or oscillation. ("de-Q") the resonant effects of the device bond wires and surrounding parasitic board capacitance. Typically, 25 series resistors (size 0402) adequately de-Q the input system without a significant decrease in ac performance. Figure 13 illustrates the value of adding input and output series resistors to help desensitize the resonant effects of board parasitics. Overshoot and undershoot can be significantly reduced with the simple addition of RIP and ROP.
1.5 NO RIP OR ROP
AGND
1 10 9 8
1.0 ROP = 25 0.5
VOLTAGE (V)
ROP
3 4
RT COPLANAR WAVEGUIDE OR STRIP RT
2
RIP
Hi-Z
7
0
RIP = ROP = 25
RIP
5 6
ROP
-0.5
RG
AGND
-1.0
-1.5
Figure 12. General Description of Recommended Board Layout for High-Z Load Conditions
TRANSMISSION LINE EFFECTS
0
1
2 TIME (ns)
3
4
Figure 13. Step Response Characteristics with and without Input and Output Parasitic Suppression Resistors
CHARACTERIZATION SETUP
As noted, stray transmission line capacitance, in combination with package parasitics, can potentially form a resonant circuit at high frequencies, resulting in excessive gain peaking. RF transmission lines connecting the input and output networks should be designed such that stray capacitance is minimized. The output single-ended source impedance of the AD8351 is dynamically set to a nominal value of 75 . Therefore, for a matched load termination, the characteristic impedance of the output transmission lines should be designed to be 75 . In many situations, the final load impedance may be relatively high, greater than 1 k. It is suggested that the board be designed as shown in Figure 12 for high impedance load conditions. In most practical board designs, this requires that the printed-circuit board traces be dimensioned to a small width (~5 mils) and that the underlying and adjacent ground planes are far enough away to minimize capacitance. Typically the driving source impedance into the device will be low and terminating resistors will be used to prevent input reflections. The transmission line should be designed to have the appropriate characteristic impedance in the low-Z region. The high impedance environment between the terminating resistors and device input pins should not have ground planes underneath or near the signal traces. Small parasitic suppressing resistors may be necessary at the device input pins to help desensitize
The test circuit used for 150 and 1 k load testing is provided in Figure 14. The evaluation board uses balun transformers to simplify interfacing to single-ended test equipment. Balun effects need to be removed from the measurements in order to accurately characterize the performance of the device at frequencies exceeding 1 GHz. The output L-pad matching networks provide a broadband impedance match with minimum insertion loss. The input lines are terminated with 50 resistors for input impedance matching. The power loss associated with these networks needs to be accounted for when attempting to measure the gain of the device. The required resistor values and the appropriate insertion loss and correction factors used to assess the voltage gain are provided in Table II.
Table II. Load Conditions Specified Differentially
Load Condition 150 1 k
R1 43.2 475
R2 86.6 52.3
Total Insertion Loss 5.8 dB 15.9 dB
Conversion Factor 20 log (S21) to 20 log (AV) 7.6 dB 25.9 dB
RS 50 BALANCED SOURCE
RT 50
50 CABLE
0.1nF
100nF
R1
50 CABLE
AD8351 DUT 0.1nF
50 CABLE
R2 RLOAD
50 CABLE
50 50 TEST EQUIPMENT
RS 50
RT 50
100nF
R1
R2
50
Figure 14. Test Circuit
REV. B
-13-
AD8351
EVALUATION BOARD
An evaluation board is available for experimentation. Various parameters such as gain, common-mode level, and input and output network configurations can be modified through minor resistor changes. The schematic and evaluation board artwork are presented in Figures 15, 16, and 17.
P1
VCOM
W1 R18 0 R6 OPEN C3 0.1 F R7 0 R3 OPEN J1 RF_IN+ J2 RF_IN- T1 R2 24.9
R17 0
ACOM
ENBL
VPOS
AGND
VPOS
AD8351
1 PWUP
VOCM 10 VPOS 9 R15 C6
C2 100nF R11 R10 61.9 1:1 ETC1-1-13 (MACOM)
C4 R5 100nF 0 R1 100
2 RGP1 3 INHI 4 INLO 5 RGP2
R13 OPEN T2 J3 RF_OUT+ J4 RF_OUT- R14 0
OPHI 8 0 OPLO 7 COMM 6 R16 0 R9 C7 100nF 61.9 100nF 61.9
1:1 ETC1-1-13 (MACOM) R12 0 R4 24.9
R8 C5 100nF 0
10 PIN mSOIC
J5 TEST IN2
C10 100nF T3 T4
J6 TEST OUT2
1:1 ETC1-1-13 (MACOM)
C9 100nF
1:1 ETC1-1-13 (MACOM)
Figure 15. Evaluation Board Schematic
Figure 16. Component Side Layout
Figure 17. Component Side Silkscreen
-14-
REV. B
AD8351
Table III. Evaluation Board Configuration Options
Component P1-1, P1-2, VPOS, AGND P1-3 W1, R7, P1-4, R17, R18
Function Supply and Ground Pins. Common-Mode Offset Pin. Allows for monitoring or adjustment of the output common-mode voltage. Device Enable. Configured such that switch W1 disables the device when Pin 1 is set to ground. Device can be disabled remotely using Pin 4 of header P1. Input Interface. R3 and R12 are used to ground one side of the differential drive interface for single-ended applications. T1 is a 1-to-1 impedance ratio balun used to transform a single-ended input into a balanced differential signal. R2 and R4 are used to provide a differential 50 input termination. R5 and R8 can be increased to reduce gain peaking when driving from a high source impedance. The 50 termination provides an insertion loss of 6 dB. C4 and C5 are used to provide ac coupling. Output Interface. R13 and R14 are used to ground one side of the differential output interface for single-ended applications. T2 is a 1-to-1 impedance ratio balun used to transform a balanced differential signal into a single-ended signal. R9, R10, and R11 are provided for generic placement of matching components. R15 and R16 allow additional output series resistance when driving capacitive loads. The evaluation board is configured to provide a 150 to 50 impedance transformation with an insertion loss of 9.9 dB. C4 through C7 are used to provide ac coupling. Gain Setting Resistor. Resistor R1 is used to set the gain of the device. Refer to TPC 2 when selecting gain resistor. When R1 is 100 , the overall system gain of the evaluation board will be approximately -6 dB. Power Supply Decoupling. The supply decoupling consists of a 100 nF capacitor to ground. Common-Mode Offset Adjustment. Used to trim common-mode output level. By applying a voltage to Pin 3 of header P1, the output commonmode voltage can be directly adjusted. Typically decoupled to ground using a 0.1 F capacitor. Calibration Networks. Calibration path provided to allow for compensation of the insertion loss of the baluns and the reactance of the coupling capacitors.
Default Condition Not Applicable Not Applicable W1 = Installed R7 = 0 (Size 0603) R17 = R18 = 0 (Size 0603) R2 = R4 = 24.9 (Size 0805) R3 = Open (Size 0603) R5 = R8 = R12 = 0 (Size 0603) C4 = C5 = 10 0 nF (Size 0603) T1 = MacomTM ETC1-1-13 R9 = R10 = 61.9 (Size 0603) R11 = 61.9 (Size 0603) R13 = Open (Size 0603) R14 = 0 (Size 0603) R15 = R16 = 0 (Size 0402) C4 = C5 = 100 nF (Size 0603) C6 = C7 = 100 nF (Size 0603) T2 = Macom ETC1-1-13 R1 = 100 (Size 0603)
R2, R3, R4, R5, R8, R12, T1, C4, C5
R9, R10, R11, R13, R14, R15, R16, T2, C4, C5, C6, C7
R1
C2 R6, C3, P1-3
C2 = 100 nF (Size 0805) R6 = 0 (Size 0603) C3 = 0.1 F (Size 0805)
T3, T4, C9, C10
T3 = T4 = Macom ETC1-1-13 C9 = C10 = 100 nF (Size 0603)
REV. B
-15-
AD8351
OUTLINE DIMENSIONS 10-Lead Mini Small Outline Package [MSOP] (RM-10)
Dimensions shown in millimeters
3.00 BSC
10
6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 1.10 MAX 8 0 0.80 0.60 0.40
SEATING PLANE
0.23 0.08
COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA
Revision History
Location 2/04--Data Sheet changed from REV. A to REV. B. Page
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3/03--Data Sheet changed from REV. 0 to REV. A.
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Change to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
-16-
REV. B
C03145-0-2/04(B)

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